1. Technical Field
This invention relates in general to integrated semiconductor chip timing or clock circuitry and, more particularly, to a digital network for reducing or eliminating clock latency created on chip by an internal clock generator, and thereby reducing clock skew between semiconductor chips in a multichip system.
2. Background Art
Almost all semiconductor microprocessor and logic chips receive an external clock signal. The external signal is often reshaped in a clock generator, or at least buffered in a logic tree for distribution across the chip. These generators/buffers introduce a delay between the external clock and the internal clock distributed on chip. This delay is termed "clock latency." The clock latency can vary significantly with process, temperature and voltage variations. The total delay between an externally generated crystal oscillator and the internal circuitry of a semiconductor chip can be in the order of several nanoseconds.
The clock path is often one of the limiting paths affecting overall achievable system speed. The clock path has a nonzero delay, and hence delay tolerances associated with the manufacturing, temperature and supply voltage. In many cases where the clock path limits overall system performance, the delay tolerance in the clock path directly impacts the system cycle time one for one. CMOS processes have especially wide tolerances. Clock paths can vary from best case to worst case by as much as 3 times, for example, a ten nanosecond clock path can vary from five to fifteen nanoseconds. Hence the designer must account for this uncertainty in the clock by decreasing the system clock speed. This causes the entire system performance to suffer.
Further, clock latency can vary significantly between semiconductor chips within a given system. For example, a multichip semiconductor system may have a best case to worst case chip clock latency of from four to ten nanoseconds. This difference between worst and best chip clock latencies comprises a clock skew between the different modules of the system. The clock skew also operates to limit system performance. In order for a design to be manufacturable, the design must be able to operate over the tolerances associated with the final product's environment and manufacturing process. If the design cannot operate within these tolerances, then screens must be inserted to differentiate products that do not operate when manufactured from those that do. Screening decreases yield which increases the cost of the final product.
The alternative to screening is to relax the product performance standards until the design can meet the temperature, power supply and manufacturing variations present in the system, which is an equally undesirable alternative.
Therefore, an on chip clock timing circuit is desirable for improved semiconductor chip and semiconductor system performance, and in particular, for reducing or eliminating internal clock latency and reducing clock skew between chips of a multichip system.